A strong market trend for embedded systems and FPGAs is to get more and more compute-intensive tasks, which often include video-processing, motor control or digital processing in general.
Join us for these two 90 minute webinars, that will include a presentation on Tuesday 19th October and a demonstration on Wednesday 20th October.
- Start Time: 14:00 CEST on both days
- Presenter: Miroslaw Dybizbanski
Both sessions will be hosted in Polish and will show an approach on how one can develop on an algorithmic level using C/C++, test the code and afterwards combine this with the parallel nature of the FPGA. In these sessions we will discuss the following areas:
- Introduction and background: Microchip FPGAs
- Highlevel synthesis overview: why, who and how?
- How to use SmartHLS for Highlevel synthesis